1. Field of the Invention
The present invention relates to an analog-to-digital converter for converting an analog signal into a digital signal.
2. Description of the Related Art
As analog-to-digital converters (hereinafter, referred to as “A/D converters”) converting analog signals into digital signals, a pipeline A/D converter has been known, which performs an analog to digital conversion (hereinafter, referred to as an “A/D conversion”) in each stage while sending signals in pipeline to subsequent stages (see, for example, Japanese Patent Laid-Open No. 2004-214905).
Further, a cyclic A/D converter which is configurable with a smaller number of devices than the pipeline A/D converter has also been known (see, for example, Japanese Patent No. 3046005).
As disclosed in, for example, Japanese Patent Laid-Open No. 2004-214905, in these A/D converters, after the analog signals are sampled and held in a sample-and-hold circuit, the A/D conversion is performed by repeating conversion stages.
In each conversion stage, a residual signal calculated in the previous stage is used to calculate an A/D conversion result of the residual signal, and also a new residual signal. Then, the A/D conversion result is sent to a digital synthesis circuit, while the new residual signal is sent to the next stage. The calculation of a residual signal is called an MDAC (Multiplying Digital to Analogue Conversion) calculation.
As disclosed in, for example, FIG. 3 of Japanese Patent Laid-Open No. 2004-214905, each conversion stage includes a sub-A/D converter, and an MDAC circuit. The MDAC circuit calculates the residual signal.
The MDAC circuit in FIG. 3 of Japanese Patent Laid-Open No. 2004-214905 is, specifically, configured by a circuit having a capacitor as disclosed in FIG. 5 of Japanese Patent Laid-Open No. 2004-214905. In a circuit disclosed in FIG. 5 of Japanese Patent Laid-Open No. 2004-214905, after the residual signal calculated in a previous stage is sampled and held in a capacitor as a charge, an MDAC calculation is performed.
Here, in order to increase the accuracy of the A/D conversion, it is necessary to increase the accuracy of calculation of an A/D conversion result and a residual signal in each conversion stage. Since both the A/D conversion result and the residual signal are calculated by using a residual signal calculated in the previous conversion stage, it is necessary to cause a sample-and-hold accuracy of the residual signal calculated in the previous conversion stage to converge to a certain range.
That is, in order to increase the accuracy of the A/D conversion, a settling time for the sample-and-hold accuracy of the residual signal to converge to a certain range is necessary. This requires some convergence time.
As means to correct an error in A/D conversion on each conversion stage, an A/D converter which corrects an error in digital bit data obtained through an A/D conversion has been also provided (see, for example, Japanese Patent Laid-Open No. 2003-174364).
In this A/D converter, an A/D conversion result is an output in binary code having 1.5 bits of information and has 0.5 bits of redundancy. Since the A/D converter has the redundancy, the accuracy requirement of an A/D conversion part is relaxed compared with that of an A/D converter having no redundancy.
However, even using this method, the problem still remains that sampling is still necessary to output a residual signal to a subsequent stage, and a certain amount of settling time is required.